A liquid crystal display device includes a TFT substrate in which pixels each having a pixel electrode, a thin film transistor (TFT), and the like are arranged in a matrix form. Further, a counter substrate is disposed opposite to the TFT substrate, in which color filters and the like are formed at positions corresponding to the pixel electrodes of the TFT substrate. A liquid crystal is interposed between the TFT substrate and the counter substrate. Then, the light transmittance is controlled by liquid crystal molecules in each pixel to form an image.
The use of liquid crystal display devices is growing in various fields due to its flatness and lightweight. Small-sized liquid crystal display devices are widely used in mobile phones and digital still cameras (DSCs). In the liquid crystal display device, the viewing angle characteristics are a problem. The viewing angle is a phenomenon in which the brightness changes or the color changes between when the display is viewed from the front and when the display is viewed from an oblique direction. The viewing angle characteristics are excellent in the in-plane switching (IPS) mode for driving liquid crystal molecules by the electric field in the horizontal direction.
There are many different types of IPS mode. For example, a common electrode is formed in a planar shape, on which a pixel electrode having a slit is provided with an insulating film interposed therebetween, to rotate liquid crystal molecules by the electric field generated between the pixel electrode and the common electrode. This type can increase the light transmittance, and is now a mainstream IPS mode. An organic passivation film is used for flattening the base on which the common electrode is formed. However, the organic passivation film is highly hygroscopic and absorbs water from the air when it is left outside. Then, in the film formation, the water absorbed by the organic passivation film is released during heat treatment. This affects the film formed on the organic passivation film, causing it to peel off.
As a method to solve such a problem, JP-A No. 271103/2009 describes a configuration in which an interlayer insulating film is formed on an organic passivation film on an image signal line, and a through hole is formed along the image signal line in the interlayer insulating film to allow gas present in the organic passivation film to be released from the through hole. Further, in JP-A No. 271103/2009, the through hole is covered by a transparent electrode that is electrically connected to the common electrode.
In order to describe the problem in the related art, first the cross-sectional structure of an IPS liquid crystal display device will be described. FIG. 9 is a cross-sectional view showing the structure of a pixel portion of a display area 10 of the liquid crystal display device. Note that the cross-sectional view of FIG. 9 is an example of the basic structure, and does not correspond one-to-one to the figures such as FIG. 2 which is a top view of an embodiment of the present invention described below. As shown in FIG. 9, the liquid crystal display device to which the present invention is applied is a top-gate TFT using poly-Si for a semiconductor layer 103. In FIG. 9, a first base film 101 of SiN and a second base film 102 of SiO2 are formed on a glass substrate 100 by chemical vapor deposition (CVD). The role of the first base film 101 and the second base film 102 is to prevent the semiconductor layer 103 from being contaminated with impurities from the glass substrate 100.
The semiconductor layer 103 is formed on the second base film 102. In order to form the semiconductor layer 103, a-Si film is formed on the second base film 102 by CVD, which is then converted into poly-Si film by laser annealing. Then, the poly-Si film is patterned by photolithography.
Agate insulating film 104 is formed on the semiconductor film. The gate insulating film 104 is SiO2 film derived from tetraethyl orthosilicate (TEOS). This film is also formed by CVD. Then, a gate electrode 105 is formed on the gate insulating film 104. The gate electrode 105 is formed on the same layer as a scan signal 30 at the same time. For example, the gate electrode 105 is formed from MoW film. When it is necessary to reduce the resistance of the scan line 30, Al alloy is used.
The gate electrode 105 is patterned by photolithography. At the time of patterning, impurities such as phosphor or boron are doped in the poly-Si layer to form a source S or drain D in the poly-Si layer. Further, a lightly doped drain (LDD) layer is formed between a channel layer of the poly-Si layer, and the source S or drain D by using the photoresist in patterning the gate electrode 105.
Then, a first interlayer insulating film 106 is formed of SiO2 so as to cover the gate electrode 105. The role of the first interlayer insulating film 106 is to provide electrical insulation between the gate line 105 and a source electrode 107. The source electrode 107 is formed on the first interlayer insulating film 106. The source electrode 107 is connected to the pixel electrode 112 through a contact hole 130. In FIG. 9, the source electrode 107 is made wide enough to cover the TFT. The drain D of the TFT is connected to the image signal line at a point not shown.
The source electrode 107 is formed on the same layer as the image signal line at the same time. In order to reduce the resistance, AlSi alloy is used for the source electrode 107 or the image signal line. In the AlSi alloy, hillock formation occurs or Al diffuses into other layers. In order to prevent such a phenomenon, AlSi is sandwiched by a barrier layer of MoW and a cap layer. Alternatively, Mow or MoCr may be used instead of using Al.
The source electrode 107 and the source S of the TFT are connected to each other through the contact hole 130 formed in the gate insulating film 104 and the first interlayer insulating film 106. An inorganic passivation film 108 is formed and covers the source electrode 107 so as to protect the entire TFT. Similarly to the first base film 101, the inorganic passivation film 108 is formed by CVD.
An organic passivation film 109 is formed so as to cover the inorganic passivation film 108. The organic passivation film 109 is formed of a photosensitive acrylic resin. Examples of the material of the organic passivation film, in addition to the acrylic resin, are a silicone resin, epoxy resin, and polyimide resin. The organic passivation film 109, which has a role of a flattening film, is made thick. The thickness of the organic passivation film 109 is 1 to 4 μm, and in most cases, about 2 μm.
The contact hole 130 is formed in the inorganic passivation film 108 and in the organic passivation film 109 to provide electrical continuity between a pixel electrode 110 and the source electrode 107. The photosensitive resin used as the organic passivation film 109 is applied and then exposed. In this way, only the portion exposed by light is dissolved with a specific developer. In other words, when the photosensitive resin is used, the formation of photoresist can be omitted. After the contact hole is formed in the organic passivation film 109, the organic passivation film 109 is annealed at about 230° C. Thus, the organic passivation film 109 is completed.
The organic passivation film 109 is dry etched using the resist as a mask, in order to form the contact hole in the inorganic passivation film 108. In this way, the contact hole 130 is formed to provide electrical continuity between the source electrode 107 and the pixel electrode 110.
The top surface of the organic passivation film 109 formed as described above is flat. Amorphous indium-tin-oxide (ITO) is deposited by sputtering on the top of the organic passivation film 109, and then patterned using photoresist. Then, the ITO is etched by sulfuric acid to pattern the common electrode 110. The common electrode 110 is formed in a planner shape, avoiding the contact hole 130. Then, the ITO is polycrystallized by annealing at 230° C. in order to reduce the electrical resistance. The common electrode 110 is formed of ITO which is a transparent electrode. The thickness of the common electrode 110 is, for example, 77 μm
Then, a second interlayer insulating film 111 is formed by CVD so as to cover the common electrode 110. At this time, the temperature condition of CVD is about 230° C., which is called low temperature CVD. Then, the second interlayer insulating film 111 is patterned by photolithography process. In FIG. 9, the second interlayer insulating film 111 does not cover the side wall of the contact hole 130. However, it is also possible that the second interlayer insulating film 111 covers the side wall of the contact hole 130.
The other films, such as the first base film 101 and the inorganic passivation film 108 are formed by CVD at a temperature of 300° C. or more. In general, the higher the temperature at which a CVD film and the like is formed the greater the adhesion to the base film. However, the organic passivation film 109 has been formed below the second interlayer insulating film 111. Thus, the characteristics of the organic passivation film 109 may be changed when the temperature is 230° C. or higher. For this reason, the second interlayer insulting film 111 is formed by low temperature CVD. When the second interlayer insulating film 111 is formed by low temperature CVD, there is a problem with the adhesion of the organic passivation film 109 to the other film, in particular to the common electrode 110 or the second interlayer insulating film 111.
The pixel electrode 112 having a slit 115 is formed by sputtering the amorphous ITO on the second interlayer insulating film 111 through a photolithography process. The pixel electrode 112 is connected to the source electrode 107 through the contact hole 113. When a signal voltage is applied to the pixel electrode 112, electric field lines are generated between the common electrode 110 and the pixel electrode 112 through the slit 115. The electric field rotates the liquid crystal molecules 301, thereby controlling the transmittance of light from a backlight for each pixel to form an image. The pixel electrode 112 is formed of ITO which is a transparent conductive film. The thickness of the pixel electrode 112 is, for example, in the range of 40 nm to 70 nm. An oriented film 113 is formed so as to cover the pixel electrode 112.
A counter substrate 200 is provided with a liquid crystal layer 300 interposed between the TFT substrate 100 and the counter substrate 200. A color filter 201 is formed within the counter substrate 200. The color filter 201 includes color filters of red, green, and blue in each pixel to form a color image. A black matrix 202 is formed between the color filters 201 to increase the contrast of the image. Note that the black matrix 202 also has a role as a light shielding film of the TFT to prevent the photocurrent from flowing into the TFT.
An overcoat film 203 is formed so as to cover the color filters 201 and the black matrix 202. The surface of the color filters 201 and the black matrix 202 is rough. Thus, the surface is flattened by the overcoat film 203. The oriented film 113 is formed on the overcoat film 203 for the initial orientation of the liquid crystal molecules. Note that FIG. 2 shows the case of the IPS, so that a counter electrode is formed on the side of the TFT substrate 100 but not on the side of the counter substrate.
As shown in FIG. 9, in the case of the IPS, the conductive film is not formed inside the counter substrate 200. As a result, the potential of the counter substrate 200 becomes unstable. In addition, external electromagnetic noise enters the liquid crystal layer 300 and affects the image. These problems eliminate by forming an external conductive film 210 on the outside of the counter substrate 200. The external conductive film 210 is formed by sputtering the ITO which is the transparent conductive film.
As described above, the second interlayer insulating film formed on the organic passivation film is deposited by low temperature CVD at about 230° C. Thus, the adhesion of the second interlayer insulating film to the base film is low. The organic passivation film, which is formed below the second interlayer insulating film, absorbs water from the air when it is left outside. Then, when the organic passivation film is annealed to form various films on the organic passivation film, the water absorbed by the organic passivation film is released. At this time, the second interlayer insulating film peels off due to its low adhesion.
In order to solve the above problem, JP-A No. 271103/2009 describes a configuration in which a thin through hole is formed in the second interlayer insulating film and along the image signal line, so that the water absorbed by the organic passivation film is let out from the through hole. Further, in JP-A No. 271103/2009, the through hole is covered by the ITO film. The ITO film is electrically connected to the common electrode so as to have the shielding effect.
However, JP-A No. 271103/2009 has the following problem. That is, the second interlayer insulating film is formed by low temperature CVD, so that the film structure is less precise than the film structure formed by high temperature CVD. Thus, when the contact hole is formed along the image signal by etching, the width of the though hole is not stabilized because of the unstable etching rate. As a result, the through hole is very likely to reach the pixel electrode. When the through hole reaches the pixel electrode, the disturbance of the electric field occurs in this portion of the pixel electrode, in which the liquid crystal molecules may not be controlled adequately. As a result, light leakage or other failure occurs. In addition, when the through hole is covered by the ITO film electrically connected to the common electrode, the pixel electrode and the common electrode are electrically connected to each other. As a result, the pixel is faulty.
Another problem of JP-A No. 271103/2009 is that when the through hole is formed in the second interlayer insulating film, its effect is reduced by covering the through hole formed along the image signal line by the ITO. In other words, also when the pixel electrode of ITO is formed on the second interlayer insulating film, the ITO film is annealed at 230° C. to reduce the resistance of the ITO. At the same time, the oriented film is also annealed to be imidized. Thus, the water absorbed by the organic passivation film is released when the ITO and oriented films are formed. For this reason, it is necessary to effectively release the water from the through hole formed in the second interlayer insulating film.